1. Field of the Invention
This invention relates generally to an automatic phase-controlled oscillator circuit, and more particularly relates to an automatic phase-controlled oscillator circuit suitable for generating a clock pulse to be synchronized with the varying frequency of a played back or received digital signal.
2. Description of the Prior Art
It is known in the art to use a phase-locked loop (PLL) circuit to generate a clock signal which is synchronized with a played back or received digital signal so that the latter can be converted to analog form. In the recording and playing back of a digital signal on magnetic tape by means of a video tape recorder (VTR) or similar apparatus, it has been previously proposed to incorporate a tuning circuit in advance of the input of such a PLL circuit to increase the signal-to-noise ratio (SNR) of the played back or received digital signal, and to assure that the capture range of the PLL circuit is adequate. If such a combination of PLL circuit and tuning circuit is used, then in a normal playback mode in which the tape speed of the VTR is the same as that which was used during recording, reliable synchronization of the PLL circuit with the played back digital signal can be established. However, in a playback mode other than the normal mode, wherein the tape speed is different from that used during recording, for example, in a low-speed playback mode such as a slow or still-picture mode, or in a high-speed playback mode such as a double-speed mode or a so-called search mode operation, the frequency of the reproduced digital signal varies, and, as a result, the output from the tuning circuit is reduced or is shifted in phase. Consequently, such a proposed arrangement has the disadvantage that the PLL circuit does not remain stably locked in phase with the reproduced digital signal.
While this disadvantage could be avoided by omitting the tuning circuit, at least when an other-than-normal playback mode is selected, the SNR of the reproduced signal which is used as a reference signal for the PLL becomes degraded, and the capture range of the PLL circuit is concomitantly narrowed, so that the PLL circuit does not easily lock in with the reproduced digital signal.